Semiconductor Environmental Testing: The Standards Stack Every Reliability Engineer Needs to Know

The qualification package was complete. Temperature cycling: 1,000 cycles, JESD22-A104, Condition B. Humidity life: 1,000 hours at 85°C/85%RH, JESD22-A101. HAST: 96 hours, JESD22-A110. Every test had been run. Every test had passed. The product was ready for production release.

Then the customer's reliability engineer looked at the chamber calibration records and asked one question: what was the DUT temperature at the soak extremes, and how was it measured?

The test lab had logged air temperature. Not DUT temperature. For JESD22-A104 Condition B — −55°C to +125°C — the standard requires that the specimen reach the nominal temperature during each soak. The air had reached it. Nobody had verified that the packages had.

The qualification had to be repeated. Six weeks. One question.

Why JEDEC JESD22 is a family of standards, not a single document

JEDEC JESD22 is commonly referenced as if it were one standard. It is not. It is a family of more than 40 individual test methods, each covering a distinct stress type, published and maintained separately by the JC-14 Reliability Committee. When a datasheet or qualification plan references "JESD22," it is meaningless without a method suffix — the information content of "tested per JESD22" is approximately zero.

The methods that drive the majority of semiconductor environmental qualification fall into four categories. Understanding which category a test belongs to determines what the chamber needs to do — and what substitutions the standard does and does not permit.

JESD22-A104: the test most labs run incorrectly

JESD22-A104 is the most widely referenced method in the family and the one most frequently run with a detail that invalidates the result. The standard specifies temperature cycling — controlled ramp, single zone — and it is explicit about one thing that the test community often overlooks: air-to-air or liquid-to-liquid thermal shock chambers shall not be substituted for thermal cycling chambers, because the ramp rate of the DUT is important and too-fast a rate can produce unrealistic damage during interconnect testing.

This note, which appears in JESD22-A104E and F as a numbered NOTE, has direct implications for how the test must be run and how the chamber must be specified. It is not advisory. It is a prohibition on a substitution that would otherwise seem equivalent to a non-specialist.

The practical consequence: a thermal shock chamber — two zones, transfer in under 30 seconds — cannot be used to run JESD22-A104 even if it can achieve the same temperature extremes. The failure modes targeted by cycling (CTE mismatch fatigue) depend on a controlled ramp rate that allows the package to respond thermally in a representative way. Thermal shock chambers stress the package differently, activating brittle fracture mechanisms that A104 is not designed to find.

What the standard actually requires from the chamber

JESD22-A104 specifies test conditions, not chamber specifications. The conditions drive the chamber requirements — and the requirements are more specific than most procurement processes acknowledge.

The standard defines several test conditions, designated by letter. The most commonly used are Condition B (−55°C to +125°C) and Condition G (−40°C to +125°C). Both specify that the specimen must reach the nominal temperature during each soak period. Not the air. The specimen.

For small semiconductor packages — a quad-flat-no-lead in 5mm × 5mm — the thermal mass is negligible. The air temperature and the package temperature are effectively the same within seconds. For larger assemblies — a flip-chip BGA on a test board, or a power module with copper baseplate — the thermal mass is significant, and the time required for the specimen to reach soak temperature may be considerably longer than the chamber's air-only settling time.

Typical component-level temperature cycle rates are in the range of 1 to 3 cycles per hour. At 2 cycles per hour with a standard soak mode, each soak period is approximately 10–15 minutes. For most IC packages, this is adequate. For a power module with 200g of copper, it may not be — and the standard's requirement that the specimen reach nominal temperature is what matters, not the cycle rate per se.

The 85/85 test and what it demands from the chamber

JESD22-A101 — steady-state temperature-humidity bias — is the test most commonly referred to as "85/85." The conditions are 85°C and 85% relative humidity, applied simultaneously with electrical bias, for a minimum of 1,000 hours. The failure mechanism is moisture ingress: penetration through the encapsulant or along the interface between the moulding compound and the metallic conductors.

The chamber requirements for A101 are fundamentally different from A104. Where A104 needs temperature cycling capability and a controlled ramp, A101 needs sustained precision at a single set point over a test duration measured in weeks. At 85°C/85% RH, the chamber is running a combined temperature and humidity condition that most standard climatic chambers can achieve — but sustaining it for 1,000 hours with adequate electrical feedthroughs for bias, and maintaining calibrated humidity control throughout, is where most failures occur.

Humidity accuracy drifts. Sensors foul. Deionised water systems require maintenance. A climatic chamber that passes its initial IQ/OQ at 85°C/85% RH in week one may be running at 83% RH by week six if the humidity sensor has drifted and the calibration interval is annual. The standard requires the conditions to be maintained throughout the test — not just at the start.

Advanced packaging and the qualification gap

The JESD22 family was written primarily for conventional plastic-encapsulated ICs. The industry has moved significantly beyond that. Today, reliability must also account for advanced packaging — 2.5D/3D, fan-out, chiplets — and wide-bandgap (SiC/GaN) power devices with higher junction temperatures and field strengths.

For 2.5D packages — a chiplet on an interposer, or a high-bandwidth memory stack — the thermal cycling qualification presents a problem that the standard does not fully address. The CTE mismatch between silicon, the interposer, and the PCB substrate creates a more complex stress state than a conventional BGA, and the cycling conditions that reliably find solder joint failures in conventional packages may underqualify or overqualify advanced package interconnects.

The practical response from most qualification engineers has been to run A104 conditions with monitoring: thermocouple attachments at multiple points on the assembly, electrical daisy-chain monitoring during the test rather than just at interim readout intervals, and failure analysis on all non-conforming results rather than treating them as outliers. This doesn't change what the standard requires — it adds the observability that advanced packages need to generate meaningful data.

For SiC and GaN power devices, the issue is junction temperature range. A device rated to 175°C junction temperature under normal A104 Condition B cycling (-55°C to +125°C) is not being stressed to its actual operating envelope. Some manufacturers have moved to Condition J (−55°C to +150°C) or custom conditions, but the chambers needed for sustained operation at +150°C require a heater specification — and a materials specification for everything inside — that standard cycling chambers running to +125°C do not need to meet.

The DUT temperature measurement that decides whether your qualification is valid

Return to the opening scenario. The test was run. The air temperature was logged. The packages may or may not have reached nominal temperature during each soak.

JESD22-A104 is explicit: the specimen shall reach the required nominal temperature during the soak time. For small packages at standard cycle rates, this is almost always true without verification. For larger assemblies, boards, or modules — or for any application where a customer or auditor may later question the qualification — the only defensible answer is a thermocouple attached to the DUT, logging package temperature throughout the test.

JEP 140 (Beaded Thermocouple Temperature Measurement of Semiconductor Packages) and JEP 153 (Characterisation and Monitoring of Thermal Stress Test Oven Temperatures) both exist specifically to address this. They are referenced normatively in JESD22-A104. If your qualification records don't include DUT temperature data for anything beyond a minimal package — and your chamber was running air-only thermocouples — the qualification has a documented gap that a sufficiently thorough auditor will find.

Choosing the chamber for a semiconductor qualification programme

A semiconductor reliability laboratory running a full JESD22-based qualification suite needs at minimum three distinct chamber types. They are not interchangeable, and a laboratory that tries to use one chamber for all three will run at least one test incorrectly.

First, a thermal cycling chamber for JESD22-A104. This is a single-zone chamber with controlled ramp rates. The JESD22-A104 temperature range to −55°C is not a particularly demanding specification — most cycling chambers can reach it. What matters is ramp rate control, uniformity at the DUT location, and the ability to accommodate test boards with electrical feedthroughs for in-situ monitoring.

Second, a climatic chamber — temperature plus humidity — for JESD22-A101. The 85°C/85% RH condition is within the range of most climatic chambers. The demanding requirement is sustained accuracy over 1,000 hours and the provision of electrical feedthroughs for bias. Humidity sensor calibration and deionised water supply management are the maintenance items that most labs underestimate for long-duration tests.

Third, a HAST chamber for JESD22-A110. HAST is a pressure vessel — a fundamentally different piece of equipment from either of the above. It operates at elevated pressure as a consequence of the elevated temperature (130°C at 85% RH generates ~2.3 atmospheres absolute), and it requires pressure-rated feedthroughs, a safety relief system, and a maintenance programme appropriate to pressure equipment.

For manufacturers of power semiconductors running Condition J or custom high-temperature profiles, the cycling chamber specification needs additional attention: materials rated to +150°C, heater capacity to sustain that temperature against the chamber's insulation losses, and a uniformity survey at the actual test temperature, not just at the standard +125°C reference point.

The complete chamber selection guide covers the specification process in detail. For the standards that govern automotive electronics qualification — which overlaps significantly with semiconductor reliability testing — the AEC-Q100 and AEC-Q200 article covers what changes when the application is automotive-grade.