The engineer had cited JESD22-A104 in seventeen test plans. He had never read it. He had read summaries of it, slides about it, blog posts explaining the key conditions. He knew the temperature ranges. He knew the cycle counts. He thought he knew the standard.
The audit found three non-conformances. All three were in sections he had assumed were procedural boilerplate. None were in the parts he had memorised.
JESD22-A104 is not a long standard. The current revision runs to fewer than twenty pages of technical content. But it contains more explicit prohibitions than most engineers who cite it have encountered — because most engineers who cite it have not read it.
What JESD22-A104 actually governs
JESD22-A104 is a JEDEC standard for temperature cycling of semiconductor components. It specifies how to cycle a component between temperature extremes to reveal package-level reliability failures — solder joint fatigue, intermetallic growth, via cracking, and delamination.
What it does not govern: wafer-level testing, burn-in, humidity exposure, or mechanical shock. Engineers who use JESD22-A104 as a catch-all reference for environmental testing of semiconductors are citing the wrong document for most of what they are testing.
NOTE 2: the substitution prohibition
NOTE 2 of JESD22-A104 reads, in full:
Three words carry the entire weight: should not be substituted. Not "is less efficient." Not "may require additional verification." Should not.
The physics: a thermal shock chamber transfers the DUT between pre-conditioned zones in under twenty seconds. The DUT surface temperature changes faster than the interior can follow — creating a thermal gradient that does not exist in field conditions. The failure mode produced by thermal shock is different from the failure mode JESD22-A104 is designed to reveal.
Running a JESD22-A104 programme in a thermal shock chamber produces data. It does not produce JESD22-A104 data.
The soak criteria most test plans get wrong
JESD22-A104 specifies that soak time is measured from the point at which the device under test reaches the required temperature — not from when the chamber air reaches it.
A DUT with significant thermal mass lags the chamber air by several minutes at each extreme. A chamber that reaches −55°C in three minutes may take eight to twelve additional minutes before a high-mass DUT stabilises. A test plan that specifies soak from chamber setpoint rather than DUT temperature is not compliant.
Ramp rate: the air-DUT gap
JESD22-A104 does not specify a maximum ramp rate — but NOTE 2 makes clear that the ramp rate at the DUT is important. The relevant specification is not the chamber's rated ramp rate. It is the ramp rate achieved at the DUT surface under load.
A chamber rated at 15°C/min empty may achieve 6°C/min at the DUT surface when loaded. For most JESD22-A104 applications, a DUT ramp rate between 3°C/min and 15°C/min is appropriate.
Condition selection and what it implies
JESD22-A104 defines eight standard conditions. The most common in semiconductor qualification:
Standard consumer and industrial qualification. Minimum 100 cycles; typical programmes run 500–1000.
Industrial and automotive. Required for AEC-Q100 Grade 1 and 2 qualification.
The most common automotive condition. Used in most automotive OEM qualification requirements.
For components in temperature-controlled environments. ΔT of 100K vs 140K in Condition A — significantly different acceleration factor.
The cycle count trap
JESD22-A104 specifies minimum cycle counts — typically 100 cycles as a floor. A test plan that specifies 100 cycles for a 15-year automotive application, citing the standard's minimum as justification, has confused the floor with the target.
AEC-Q100 cycle counts by grade: Grade 0 (−40°C to +150°C) — 1,000 cycles. Grade 1 (−40°C to +125°C) — 1,000 cycles. Grade 2 (−40°C to +105°C) — 500 cycles. Grade 3 (−40°C to +85°C) — 500 cycles.
What a compliant test report must contain
Chamber type declaration. The report must identify the chamber as a temperature cycling chamber — not a thermal shock chamber.
DUT temperature data. Thermocouple data from the DUT surface, or documented justification for why DUT temperature is equivalent to air temperature for the specific configuration.
Ramp rate at DUT. Derived from the DUT thermocouple data — not the chamber's rated ramp rate.
Soak time verification. Evidence that the soak timer started when the DUT reached temperature.
Condition and cycle count. The specific JESD22-A104 condition and the number of cycles completed.
The 2023 revision: what changed
JESD22-A104F was published in 2023. Condition H (−55°C / +150°C) was added for high-temperature power electronics. The soak temperature tolerance was explicitly clarified to apply to the DUT temperature, not the chamber air. NOTE 2 was retained unchanged.
If your test plan cites JESD22-A104, verify the chamber type before the test starts.
Read Case #004 →Frequently asked questions
Can a thermal shock chamber be used instead of a cycling chamber for JESD22-A104?
No. JESD22-A104 NOTE 2 explicitly states that air-to-air or liquid-to-liquid thermal shock chambers shall not be substituted for thermal cycling chambers. The ramp rate of the DUT matters for the failure mechanisms A104 targets — too-fast a rate produces unrealistic damage during interconnect testing that does not represent field conditions.
What is the difference between JESD22-A101 and JESD22-A110 (HAST), and are they interchangeable?
Both target moisture ingress failure mechanisms. A101 runs at 85°C/85% RH for 1,000 hours; A110 (HAST) accelerates this with temperature (typically 130°C) and pressure (~2.3 atm), reducing the duration to 96 hours. They are not directly interchangeable for all device types — some qualification frameworks accept HAST as a substitute for 85/85, but this requires documented justification and is not automatic.
Does JESD22-A104 require DUT temperature measurement or just chamber air temperature?
The standard requires that the specimen reach the nominal temperature during each soak period — not just the chamber air. For small packages the difference is negligible. For larger assemblies, boards, or power modules, a thermocouple on the DUT is the only way to demonstrate compliance with this requirement. JEP 140 and JEP 153 provide the measurement methodology.
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